85/2004 : Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic

RR Number

85/2004

Author(s)

Wolfgang Huber, Andreas Steininger, Martin Delvai

Abstract

Virtually all asynchronous design techniques employ pipelining to structure the data path. The classical micropipeline architecture as introduced by Sutherland provides a generic solution to this problem; it is, how- ever, not a delay insensitive approach, since handshak- ing is based on delay elements. So the question arises, whether it is possible to modify this principle and com- bine it with another method such that the resulting ar- chitecture is indeed delay insensitive. In this paper we investigate this question at the exam- ple of CAL, a design method also known as four phase logic. We propose and optimize different pipeline im- plementations and discuss their respective merits and drawbacks along with simulation results and implemen- tation experiences.

Bibtex

@techreport{ huber:2004-85,
  author =       "Wolfgang Huber and Andreas Steininger and Martin Delvai",
  title =        "Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic",
  institution =  "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  address =      "Treitlstr. 1-3/182-1, 1040 Vienna, Austria",
  type =         "Research Report",
  year =         "2004",
  number =       "85/2004"
}

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