[ main page ] [ back ]

2005 : Design of an Asynchronous Processor Based on Code Alternation Logic - Treatment of Non-Linear Data Paths

Author(s)
Martin Delvai
Abstract
The synchronous design paradigm faces some limitations: The illusion that all components inside a chip receive the (active) clock edge at the same point in time can be sustained only under a considerable hardware effort. In addition, the power consumption of a CMOS circuit is proportional to the applied clock frequency - thus the increasing clock frequency coupled with today's high integration density escalates the heating problem. In contrast, asynchronous design methods promise to solve all these problems in a natural manner: On the one hand they require only (local) handshake mechanisms instead of a global time reference. On the other hand, asynchronous methods are event-driven - hence they consume energy only when useful work has to be performed, in contrast to synchronous circuit, which are permanently triggered by the clock signal. With this motivation several asynchronous design methods were analyzed. A specific method, namely the Code Alternation Logic was selected to implement an asynchronous processor prototype. The principle of this approach is to encode the information necessary for the data flow control in the processed data itself, by defining two disjoint representations for the logical HIGH and two for the representation of LOW. To highlight that from a logical point of view both representants carry the same information we say that a signal can be coded in different phases. Since subsequent data waves are coded in alternating phases, each component inside the circuit can distinguish incoming data and associate it to a specific context. However, non-linear circuit structures disturb this alternating sequence of data waves and therefore affect the data flow control. The focus of this thesis is placed on such non-linear structures. Here, two types of non-linearity are distinguished: forward/feedback paths and selecting nodes. The first one causes that components receive signals which belong to the same context, but are coded in different phases. To overcome this problem we have to place phase inverters in a selective manner. In this work it is shown, that the placement not only depends on the circuit topology, but also on its initialization. Furthermore it is pointed out, that feedback/forward paths cause a structural regulation of the data flow. As a consequence, the performance of a circuit depends strongly on its initialization. The second source of non-linearity is constituted by nodes, which require only a subset of their inputs to generate the output (multiplexer, e.g.) and/or nodes which set only a subset of their outputs (de-multiplexer, e.g.). Consequently the parts of the circuit, which are connected to the unselected inputs/outputs of selecting nodes, loose their phase synchronization with the remaining circuit. This difficulty can be solved by using synchronizer circuits or "dummy" data. The findings of this thesis were confirmed by simulation and verified by the implementation of a hardware prototype of an asynchronous processor.
Bibtex
@phdthesis{ delvai:2005,
  author =      "Martin Delvai",
  title =       "Design of an Asynchronous Processor Based on Code Alternation Logic – Treatment of Non-Linear Data Paths",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        "2005"
}
Download
Get thesis.pdf - Adobe PDF-format, (2811.5898 KB; posted at July 09 2013)


[ main page ] [ back ]