53/2005 : A Strategy for Experimental Fault Injection into an Asynchronous Processor

RR Number

53/2005

Comment

submission to DFT05

Author(s)

Babak Rahbaran, Andreas Steininger

Abstract

With clock rates beyond 1 GHz the model of a system-wide synchronous clock is becoming difficult to maintain, therefore asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. Since any future design style will have to cope with increased rates of transient faults, robustness is one of the crucial properties. With this motivation we have set up fault-injection experiments to assess the robustness of an asynchronous microprocessor. This paper summarizes our experiences with this setup: The central problem was that traditional (synchronous) fault-injection experiments are largely based on the availability of a global clock. We identify the resulting problems for our asynchronous target and elaborate appropriate solutions, such that we can finally present and demonstrate a suitable setup.

Download