**Author(s)**- Wolfgang Huber
**Abstract**- The synchronous design technique increasingly reaches its limits: More and more functionalities are integrated on one chip causing the chip size to grow, thus effectively countervailing the reduction of feature size allowed by improved manufacturing technologies. Higher clock frequency not only requires steeper clock edges, hence increasing power consumption, but also destroys the fiction of simultaneous events on the whole chip. This abstraction of simultaneity is an essential basis for how the synchronous design paradigm solves the fundamental design problems, e.g. the formal incompleteness of the Boolean Logic. Synchronous designs tackle these fundamental problems in the time domain. However, solutions in the information domain and the so-called hybrid solution - a conjunction of both methods - are also possible. Code Alternation Logic (CAL) is a representative of a hybrid solution. Up to a certain abstraction level, CAL is delay insensitive, however, for the implementation of the basic gates, temporal restrictions apply. CAL is based on the utilization of two representations of "high" and "low" in two different phases phi0 and phi1. The representations are used alternatively, so within a sequence of data words each bit can uniquely be assigned to the corresponding data word. These four possible values are either described by a four-value single-rail signal of type CAL-logic, which is utilized for the behavioral description of the design, or by a two-value dual-rail CAL-raillogic signal. The latter is used for the hardware implementation. In contrast to the conventional synchronous design flow, our CAL design flow comprises two synthesis steps. Furthermore, the designer is supported by simulation models for different abstraction levels. Altera Apex FPGAs are used as target technology, thus LUTs are the smallest units which can be addressed. A main goal of this thesis is to analyze the delay insensitivity of a circuit implementation with CAL. For this purpose pipeline stages as well as basic gates are transformed to timed automata and analyzed with the model-checker UPPAAL. In this thesis the delay insensitive behavior of pipeline structures and the correctness of the combinational logic between these stages is proven. Up to this point hardware independent models of the basic gates are used for constructing these combinational logic functions, which operate according to the CAL rules. As a next step the implementation of the basic gates in the target technology is investigated. The limitations with respect to delay insensitivity are pinpointed and appropriate design constraints are derived. The impacts of the findings are used to improve the design flow. Furthermore, the results have allowed us designing our asynchronous processor ASPEAR. The development of an improved pipeline concept, the application of pre-compiled basic gates using Quartus, and the new library providing these gates to the synthesis tools are verified with the successful implementation of the processor.
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