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2006 : Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

Author(s)
Matthias Fuegger
Abstract
Due to conceptual problems of synchronous design methodologies, considerable effort must currently be spent on maintaining the abstraction of a discrete global time on the entire chip. This master's thesis presents the pivotal basis of an alternative design principle, which is currently investigated in the DARTS project (a cooperation between the Vienna University of Technology and Austrian Aerospace): A chip is partitioned into loosely coupled functional units, that, together, form a System-on-Chip (SoC). It is shown how the well-known clock synchronization algorithm by Srikanth and Toueg can be adopted to the peculiarities of digital hardware design and hence be used for generating a fault-tolerant distributed clock signal for each functional unit. It is formally proved that the different clock signals are not independent of each other, but satisfy certain synchronization properties (frequency bounds, bounds on maximum phase differences between different clock signals). Consequently a global SoC time can be generated from the local clock signals, which facilitates inter-functional unit communication. Finally, the feasibility of implementing the proposed algorithm directly in hardware is demonstrated via first promising results of an FPGA implementation.
Bibtex
@mastersthesis{ fuegger:2006,
  author =      "Matthias Fuegger",
  title =       "{F}ault-{T}olerant {D}istributed {C}lock {G}eneration in {VLSI} {S}ystems-on-{C}hip",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        "2006"
}
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