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53/2006 : Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs

RR Number
53/2006
Conference
IEEE East-West Design & Test International Workshop (EWDTW'06)
Author(s)
Andreas Steininger, Thomas Handl, Gottfried Fuchs, Franz Zangerl
Abstract
This paper presents our test strategy for a hardware unit that is at the heart of a fault-tolerant distributed clock generation concept for a System-on-Chip (SoC). The specific problem with testing this unit lies in its asynchronous but still sequential nature. We outline how we still manage to achieve the required test coverage for this unconventional circuit on a synchronous tester, while minimizing area overhead, performance penalties and test time.
Bibtex
@article{ steininger:2006-53,
  author =       "Andreas Steininger and Thomas Handl and Gottfried Fuchs and Franz Zangerl",
  title =        "Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs",
  journal =      "IEEE East-West Design & Test International Workshop",
  year =         "2006",
  month =        "Sep."
}
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