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61/2006 : VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

RR Number
61/2006
Conference
IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT2006)
Author(s)
Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf
Abstract
In this paper we will introduce a novel approach for the on-chip generation of a fault-tolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. We will present the underlying algorithm, point out the difficulties for the hardware implementation and will provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method we also present some measurement results from a prototype implementation.
Bibtex
@article{ ferringer:2006-61,
  author =       "Markus Ferringer and Gottfried Fuchs and Andreas Steininger and Gerald Kempf",
  title =        "{VLSI} {I}mplementation of a {F}ault-{T}olerant {D}istributed {C}lock {G}eneration",
  journal =      "IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT2006)",
  year =         "2006",
  month =        "Oct."
}
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