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69/2006 : An Efficient Test for a Transition Signalling based Up-/Down-Counter

RR Number
69/2006
Conference
The Austrian National Conference on the Design of Integrated Circuits and Systems (Austrochip 2006)
Author(s)
Matthias Fuegger, Thomas Handl, Andreas Steininger, Josef Widder, Christian T�gel
Abstract
This paper reports on a formal model for testing transition signalling logic in presence of (multiple) stuck-at faults and how this model can be applied to an Up-/Down-Counter Module. The Counter forms a key element in the fault-tolerant distributed clock generation circuit developed in the course of our DARTS (Distributed Algorithms for Robust Tick Synchronization) project, but is sufficiently general to be of interest for other transition signalling circuits, too. We point out the particular problems of testing a self-timed logic module and devise a very efficient test with 100% coverage for our Counter Module.
Bibtex
@article{ fuegger:2006-69,
  author =       "Matthias Fuegger and Thomas Handl and Andreas Steininger and Josef Widder and Christian Tögel",
  title =        "An Efficient Test for a Transition Signalling based Up-/Down-Counter",
  journal =      "The Austrian National Conference on the Design of Integrated Circuits and Systems (Austrochip 2006)",
  year =         "2006",
  month =        "Oct."
}
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