104/2006 : Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder

RR Number

104/2006

Comment

Student paper

Conference

Austrochip 2006, Vienna, Austria

Author(s)

K. Ambrosch, C. Helpa, J. Lechner, R. Leidenfrost, T. Panhofer, S. Ramberger, U. Stadler, D. Steiner, H. Trinkl, C. Widtmann, Martin Delvai, A. Platschek

Abstract

FPGAs open completely new possibilities in system design, allowing to move the border between hard- and software. This, on the one hand opens the way to tune system parameters according to specific application needs, but on the other hand is a quite complex task and an unfavourable partitioning could worsen the overall system compared to a pure software or a pure hardware implementation. In this paper we investigate the impact of different hardware/software partitioning at the example of an AES encoder. Several groups of students implemented such an AES encoder, whereas the hardware/software partitioning was not a priori given, but was chosen by each group individually. Each implementation was evaluated using an evaluation matrix, which rated design parameters such as power consumption, performance, lines of code, etc. At the end of this paper we compare all implementations and discuss the impact of the partitioning in particular.

Bibtex

@article{ ambrosch:2006-104,
  author =       "K. Ambrosch and C. Helpa and J. Lechner and R. Leidenfrost and T. Panhofer and J. Platschek and S. Ramberger and U. Stadler and D. Steiner and H. Trinkl and C. Widtmann and Martin Delvai",
  title =        "Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder",
  journal =      "Austrochip 2006, Vienna, Austria ",
  year =         "2006",
  month =        "Oct."
}

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