41/2000 : How Does Resource Utilization Affect Fault Tolerance?

RR Number

41/2000

Conference

International Symposium on Defect and Fault Tolerance in VLSI Systems

Author(s)

Christoph Scherrer, Andreas Steininger

Abstract

Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of the fail-silent “Time-Triggered Architecture” we study sources and effects of dormant faults. We identify software as being more prone to dormant faults than hardware. By means of modeling we reveal a high sensitivity of the MTTF to the existence of even a small amount of irregularly used resources. We propose on-line testing as a means of coping with dormant faults and sketch an appropriate test strategy.

Bibtex

@article{ scherrer:2000-41,
  author =       "Christoph Scherrer and Andreas Steininger",
  title =        "How Does Resource Utilization Affect Fault Tolerance?",
  journal =      "International Symposium on Defect and Fault Tolerance in VLSI Systems",
  year =         "2000",
  month =        "Oct."
}

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