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2007 : Reconfigurable Hardware Implementation of Polynomial Arithmetic over the Finite Field GF(3)

Author(s)
Hannes Prokop
Abstract
This thesis describes the design and implementation of a hardware accelerator system for arithmetics over the finite field GF(3). Starting from a given software implementation and publications describing suitable algorithms and representation techniques, a combined hardware/software solution is developed. The first chapters give an introduction into finite fields in general and the finite field with three elements GF(3) in specific. Representation techniques for binary logic are presented and possible areas of applications are discussed. Using an improved representation suggested by several authors in their publications, a system is implemented that has three parts. A hardware accelerator, a modified software program and a device driver connecting them. The hardware accelerator is designed using the hardware description language VHDL and resembles the functionality of an arithmetic routine previously implemented in software. Using reconfigurable logic in the form of a Field Programmable Gate Array (FPGA), the hardware accelerator offers high performance as well as area efficiency and is connected to the host system using a PCI expansion card. The software part of the design is based on a previous implementation and modified to exploit the computational resources of the hardware accelerator. Using state-of-the-art software, a device driver has been developed to control the hardware accelerator in a desktop or server environment. Using these three components, extensive performance measurements were conducted and the results were compared to previously existing software and hardware solutions. Bus bandwidth is identified as the biggest limiting factor of the design and solutions are suggested to bypass this problem in future works. The thesis concludes with a chapter on proposed improvements and future work.
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