23/2007 : An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip

RR Number

23/2007

Conference

19. GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Erlangen

Author(s)

Thomas Handl, Andreas Steininger

Abstract

We describe the test concept for a clock genera- tion unit that implements one instance of a distributed agreement algorithm in hardware. The challenge of testing this unit lies in its asynchronous nature. We propose a suitable partitioning of the self-timed circuit and the introduction of two scan chains whose opera- tion is carefully interlocked. In this way we can achieve a coverage of 100% for single stuck-at faults with very low overheads in term of speed penalty and test pins.

Bibtex

@article{ handl:2007-23,
  author =       "Thomas Handl and Andreas Steininger",
  title =        "An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip",
  journal =      "19. GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Erlangen",
  year =         "2007",
  month =        "Mar."
}

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