37/2007 : A Time-Triggered Network-on-Chip

RR Number

37/2007

Conference

International Conference on Field-Programmable Logic and its Applications (FPL 2007)

Author(s)

Martin Schoeberl

Abstract

In this paper we propose a time-triggered network-on-chip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature for dependable real-time systems. A regular structured NoC with a pseudo-static communication schedule allows for a high bandwidth. In this paper we argue for a simple, time-triggered NoC structure to achieve maximum bandwidth. We have implemented the proposed TT-NoC in a low-cost FPGA. The base bandwidth is 29 Gbit/s and the peak bandwidth 230 Gbit/s for eight nodes. The idea is in line with current on-chip multiprocessor designs, such as the Cell processor. The simple design of the network and the network interface easies certification of the proposed NoC for safety critical applications.

Bibtex

@INPROCEEDINGS{jop:ttnoc,
  author = {Martin Schoeberl},
  title = {A Time-Triggered Network-on-Chip},
  booktitle = {International Conference on Field-Programmable Logic and its Applications
	(FPL 2007)},
  year = {2007},
  pages = {377 -- 382},
  address = {Amsterdam, Netherlands},
  month = {August},
  url = {http://www.jopdesign.com/doc/ttnoc_fpl2007.pdf}
}

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