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57/2007 : SAFE — A Scalable Environment for Automated Transistor Level Fault Effect Analysis

RR Number
57/2007
Conference
Austrochip 2007
Author(s)
Julian Grahsl, Thomas Handl, Andreas Steininger, Gerald Kempf
Abstract
As recent trends within the testing community show, the shortcomings of the classical gate level stuck-at fault model evolve into increasingly severe issues, especially with respect to coverage and fault effect analysis. In addition, this model is not applicable to emerging design styles like transition signaling and self-timed circuits, where information is encoded both in the value and time domain. To cope with these insufficiencies, testing at transistor level can be envisioned to examine circuits much more in-depth. However, due to the higher costs and expenditure of time, this method seemed inferior to stuck-at fault testing to industrial practice until now. In this paper, we will (i) introduce a classification of transistor level faults appropriate for efficient testing and (ii) present a framework to perform transistor level fault effect analysis - based upon this classification - automatically and thus with limited efforts.
Bibtex
@article{ grahsl:2007-57,
  author =       "Julian Grahsl and Thomas Handl and Andreas Steininger and Gerald Kempf",
  title =        "SAFE — A Scalable Environment for Automated Transistor Level Fault Effect Analysis",
  journal =      "Austrochip 2007",
  year =         "2007",
  month =        "Oct."
}
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