58/2007 : SimpCon - a Simple and Efficient SoC Interconnect

RR Number

58/2007

Conference

Proceedings of the 15th Austrian Workhop on Microelectronics, Austrochip 2007

Author(s)

Martin Schoeberl

Abstract

To build a system-on-chip (SoC) a common interface standard is necessary to connect ready-to-use components (IPs) from different vendors. Today several SoC interconnect standards, such as AMBA, Wishbone, OPB, and Avalon, are in use. We show in this paper that those standards have a common drawback for on-chip interconnections: They are built on the model of a common back-plane bus that does not fit very well for on-chip interconnections. We provide a new, simple on-chip interconnect specification for the well accepted master/slave model. It is intended to provide pipelined access to devices such as on-chip peripherals and on-chip memory controller with minimum hardware resources.

Bibtex

@INPROCEEDINGS{simpcon,
  author = {Martin Schoeberl},
  title = {{SimpCon} - a Simple and Efficient {SoC} Interconnect},
  booktitle = {Proceedings of the 15th Austrian Workhop on Microelectronics, Austrochip
	2007},
  year = {2007},
  address = {Graz, Austria},
  month = {October},
  url = {http://www.jopdesign.com/doc/simpcon_austrochip2007.pdf}
}

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