71/2007 : Time-Multiplexed Multiple Constant Multiplication

RR Number

71/2007

Conference

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Author(s)

Peter Tummeltshammer, James C. Hoe, Markus Pueschel

Abstract

This paper studies area-efficient arithmetic circuits to multiply a fixed-point input value selectively by one of several preset fixed-point constants. We present an algorithm that generates a class of solutions to this time-multiplexed multiple-constant multiplication problem by “fusing” single-constant multiplication circuits for the required constants. Our evaluation compares our solution against a baseline implementation style that employs a full multiplier and a lookup table for the constants. The evaluation shows that we gain a significant area advantage, at the price of increased latency, for problem sizes (in terms of the number of constants) up to a threshold dependent on the bit-widths of the input and the constants. Our evaluation further shows that our solution is better suited for standard-cell application-specific integrated circuits than prior works on reconfigurable multiplier blocks.

Bibtex

@ARTICLE{Tummeltshammer:07,

AUTHOR = {Peter Tummeltshammer and James C. Hoe and Markus P{\"u}schel},
TITLE = {Time-Multiplexed Multiple Constant Multiplication},
JOURNAL = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
VOLUME = {26},
NUMBER = {9},
PAGES = {1551--1563},
YEAR = {2007}
}

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