88/2007 : A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture

RR Number

88/2007

Comment

Presented at the 5th IFIP Workshop on Software Technologies for Future Embedded & Ubiquitous Systems (SEUS 2007),Santorini, Greece, May, 2007

Conference

Lecture Notes in Computer Science

Author(s)

Martin Schlager, Roman Obermaisser, Wilfried Elmenreich

Abstract

In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as recently developed in DECOS (Dependable Embedded COmponents and Systems), an integrated project within the Sixth Framework Programme of the European Commission. Focusing on the interconnection between the simulated environment and the Integrated System Under Test (ISUT), our approach involves the concept of a Smart Virtual Transducer (SVT) that replaces the physical transducers of the ISUT without a probe effect on the ISUT. Our approach enables a complexity reduction for setting up an HiL simulation and supports a well-designed scalable interface to an integrated architecture. Furthermore, we support non-intrusive, deterministic interaction between the environment simulation system and the ISUT in order to guarantee reproducible test-runs. We show an exemplary application of the proposed concept by tailoring the generic components of the proposed simulation approach to an automotive park assistant system.

Bibtex

@article{ schlager:2007-88,
  author =       "Martin Schlager and Roman Obermaisser and Wilfried Elmenreich",
  title =        "A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture",
  journal =      "Lecture Notes in Computer Science",
  year =         "2007",
  month =        sep,
  volume =       "4761/2007",
  pages =        "159-170",
  note = "Presented at the 5th IFIP Workshop on Software Technologies for Future Embedded & Ubiquitous Systems (SEUS 2007),Santorini, Greece, May, 2007"
}

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