17/2008 : SAD based stereo matching using FPGAs

RR Number

17/2008

Conference

Chapter 6 of Embedded Computer Vision - Advances in Pattern Recognition Series, Springer Verlag, London, 2008

Author(s)

K. Ambrosch, Martin Humenberger, Wilfried Kubinger, Andreas Steininger

Abstract

In this chapter we present a Field Programmable Gate Array (FPGA) based stereo matching architecture. This architecture uses the Sum of Absolute Differences (SAD) algorithm and is targeted at automotive and robotics applications. The disparity maps are calculated using 450£375 input images images and a disparity range of up to 150 pixels. We discuss two different implementation approaches for the SAD and analyze their resource usage. Furthermore, block sizes reaching from 3£3 up to 11£11 and their impact on the consumed logic elements as well as on the disparity maps’ quality are discussed. The stereo matching architecture enables a frame rate of up to 599 fps by calculating the data highly parallel and pipelined. This way, a software solution optimized by using Intel’s Open Source Computer Vision Library running on an Intel Pentium 4 with 3 GHz clock frequency is 402 times outperformed.

Bibtex

@article{ ambrosch:2008-17,
  author =       "K. Ambrosch and Martin Humenberger and Wilfried Kubinger and Andreas Steininger",
  title =        "SAD based stereo matching using FPGAs",
  journal =      "Chapter 6 of Embedded Computer Vision - Advances in Pattern Recognition Series, Springer Verlag, London, 2008",
  year =         "2008",
  month =        "Oct."
}

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