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2008 : The Time-Triggered System-on-Chip Architecture

Author(s)
Christian Paukovits
Abstract
The Time-Triggered System-on-Chip (TTSoC) architecture provides a component-based design methodology, which addresses complexity management of System-on-Chip designs equipped with billions of transistors. Abstraction, determinism, and encapsulation are the means to achieve a consequent decoupling of computational components from the communication infrastructure, which entails error containment and promotes composability. This thesis presents a real implementation of the TTSoC architecture based on FPGA technology. Intellectual Property (IP)-cores contain the processing units, in which jobs of application subsystems are executed. Each IP-core has one Trusted Interface Subsystem (TISS) attached, which realizes the major part of the TTSoC architecture's core services such as the time-triggered communication service. The TISS offers these core services to the IP-cores through the Uniform Network Interface (UNI). Each pair of IP-core and attached TISS forms a micro component, which is regarded as architectural unit. Micro components are interconnected through the Time-Triggered Network-on-Chip (TTNoC). Micro components communicate with each other by means of encapsulated communication channels. Their endpoints --- the ports --- contain application-level messages, which are exchanged between micro components. The real communication within encapsulated communication channels is abstracted from the IP-core. Communication is synchronized by means of a notion of a global time base, which entails a periodic control system in order to temporally align communication. The TISS harnesses the global time base in order to determine the instants, when a communication activity takes place. Additionally, it controls the flow of messages from send port to receive port of an encapsulated communication channel. On-the-fly reconfiguration allows the TTSoC architecture to change system parameters during live operation, which is used to adapt the system to changing resource demands or environmental conditions. To let a given IP-core take part in the TTSoC architecture, a TISS causes a hardware overhead of 10 % and below on FPGA technology. The monetary costs on ASIC technology can be estimated in the magnitude of fractions of one-digit dollar cent.
Bibtex
@phdthesis{ paukovits:2008,
  author =      "Christian Paukovits",
  title =       "The Time-Triggered System-on-Chip Architecture",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        2008,
  month =       dec,
}
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