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2009 : Multiport SSRAM Controller

Author(s)
Andreas Czink
Abstract
When multiple processors are used in embedded systems, the need to access the main memory with multiple components arises. Such an access is in conflict with the fact that standard memory components often only provide one interface for access. Moreover, the single components often use different clock frequencies (for example, the clock frequencies can be given by the speed of external interfaces). This thesis presents techniques that allow access to a single SSRAM chip (which only provides one interface) from multiple components that work with different clock frequencies. Methods for signal synchronization and methods for arbitration are discussed. For signal synchronization a well-established handshake protocol is presented that then will be optimized for throughput. Beside the discussion of theoretical aspects also a controller for practical access to the SSRAM is developed. Two or three components can access the whole memory via this controller. The components use standardized interfaces (concretely: Avalon Memory Mapped Interfaces) to increase reusability of the controller. The implementation is based on FPGA technology; the language VHDL is used to specify the controller. The presented controller is discussed with regard to throughput and latency. Upper and lower bounds can be found. Knowing these bounds means that the length of memory access is WCET-analyzable. This implicates that the controller can be used in hard real-time systems.
Bibtex
@bachelorsthesis{ czink:2009,
  author =      "Andreas Czink",
  title =       "Multiport SSRAM Controller",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        "2009"
}
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