84/2009 : Coupling Asynchronous Signals into Asynchronous Logic
In this paper we will discuss methodologies of interfacing
delay-insensitive phased logic circuits. As for ordinary
synchronous designs, special measures need to
be taken into account when dealing with external asynchronous signals. In the case of phased logic, external
(single-rail) signals must be converted into a dualrail
representation, thereby not violating the internal registersí timing constraints, and at the same time maintaining delay-insensitivity. In this paper we will provide an overview to different kinds of interfaces between synchronous and asynchronous designs and develop a conversion circuit that is suitable for phased logic designs, because it maintains delay-insensitivity at the internal interface.
author = "Markus Ferringer",
title = "Coupling Asynchronous Signals into Asynchronous Logic",
journal = "Austrochip 2009",
year = "2009",
month = "Oct."
Get austrochip.pdf - Adobe PDF-format, (165.01 KB; posted at December 11 2009; )