86/2009 : FUSE - A HARDWARE ACCELERATED HDL FAULT INJECTION TOOL

RR Number

86/2009

Conference

5th Southern Conference on Programmable Logic, 2009. SPL.

Author(s)

Martin Delvai, Stefan Reichör, Marcus Jeitler

Abstract

The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this contextfault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore be re-ferred to as hardware- or software-, simulation- or emulation based techniques. In this paper we present FuSE, a single fault injection tool which covers multiple domains as well as different fault injection purposes. FuSE has been designed for usage with the SEmulator - an FPGA-based hardware accelerator. The created tool set has been fully automated for the fault injection process and only requires a VHDL description and a testbench of the circuit under test. FuSE can then perform fault injection experiments with a diagnostic resolution that is known from simulation-based approaches, but at a speed that even handles long running experiments with ease.

Bibtex

@INPROCEEDINGS{4914906,
title={FuSE - a hardware accelerated HDL fault injection tool},
author={Jeitler, M. and Delvai, M. and Reichor, S.},
booktitle={Programmable Logic, 2009. SPL. 5th Southern Conference on},
year={2009},
month={April},
volume={},
number={},
pages={89-94},
keywords={fault tolerance, field programmable gate arrays, hardware description languages, logic designFPGA-based hardware accelerator, FuSE, VHDL, digital circuit, fault tolerance validation, hardware accelerated HDL fault injection tool},
doi={10.1109/SPL.2009.4914906},
ISSN={}, }

Download

Get spl09.pdf - Adobe PDF-format, (257.52 KB; posted at December 16 2009; )