87/2009 : Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection

RR Number

87/2009

Conference

5th Doctorial Workshop on Mathematical and Engineering Methods in Computer Science

Author(s)

Marcus Jeitler, Jakob Lechner

Abstract

As transient error rates are growing due to smaller feature sizes, designing reliable synchronous circuits becomes increasingly challenging. Asynchronous logic design constitutes a promising alternative with respect to robustness and stability. In particular, delay-insensitive asynchronous circuits provide interesting properties, like an inherent resilience to delay-faults. This paper presents a new approach for comparing the robustness of synchronous and asynchronous logic. In order to ensure comparability we have developed a tool to automatically transform synchronous designs into their asynchronous counterparts while preserving structural and functional equivalence. Using a saboteur-based fault injection technique, the robustness assessment of both synchronous and asynchronous circuits can then be performed. At the example of a small-sized test design, this paper demonstrates the capabilities of the proposed approach and, based on these first results, briefly investigates the different behavior of synchronous and asynchronous circuits in the presence of faults.

Bibtex

@article{ jeitler:2009-87,
  author =       "Marcus Jeitler and Jakob Lechner",
  title =        "Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection",
  journal =      "5th Doctorial Workshop on Mathematical and Engineering Methods in Computer Science",
  year =         "2009",
  month =        "Nov."
}

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