88/2009 : Speeding up Fault Injection for Asynchronous Logic by FPGA-based Emulation

RR Number

88/2009

Conference

2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09

Author(s)

Marcus Jeitler, Jakob Lechner

Abstract

While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection against various fault types. However, results on experimental evaluation and analysis of these fault tolerance properties are scarce, mainly due to the lack of suitable prototyping platforms. Using a soft-core processor as an example, this paper shows how an off-the-shelf FPGA can be used for asynchronous Four State Logic designs, on which future fault injection experiments will be conducted.

Bibtex

@article{ jeitler:2009-88,
  author =       "Marcus Jeitler and Jakob Lechner",
  title =        "Speeding up Fault Injection for Asynchronous Logic by FPGA-based Emulation",
  journal =      "2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09",
  year =         "2009",
  month =        "Dec."
}

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