[ main page ] [ back ]

2010 : Hardware Transactional Memory for a Real-Time Chip Multiprocessor

Author(s)
Peter Hilber
Abstract
Transactional memory is an alternative to conventional lock-based synchronization. Locks are difficult to use and not composable; transactional memory off ers a simple programming model and the high concurrency desired for future multiprocessors. While actually multiple threads concurrently access shared data,the results look as if code sections (transactions) had been executed sequentially. Conflicts among concurrent transactions are automatically resolved. To our knowledge, there is currently no transactional memory system suitable for hard real-time systems on multiprocessors. Real-time transactional memory (RTTM) is a proposal of a time-predictable transactional memory for chip multiprocessors. The main goals of RTTM are a simple programming model and analyzable timing properties. Static analysis detects non-conflicting transactions, which lowers the worst-case execution time bounds. In this masterís thesis, RTTM was implemented on an FPGA and the viability of the implementation was evaluated. For time-predictable execution, RTTM is hardware-based. Each core gets a small, fully associative cache which tracks the memory accesses in a transaction. RTTM was implemented on JOP, a time-predictable chip multiprocessor directly executing Java bytecode. The basic programming interface is the @atomic method annotation. Using Java facilitates link-time transformations and the abort of conflicting transactions. The FPGA-based implementation supports small transactions suitable for synchronization in embedded real-time applications. Up to 12 cores fit on a low-cost Cyclone II FPGA running at 90 MHz with a device utilization of more than 90%. The RTTM hardware is costly due to the fully associative cache, but does not dominate the hardware resource consumption. The close relationship of the processor to the Java Virtual Machine enables some resource-saving optimizations. A part of RTTM was implemented in software in order to make the integration of the CPU nearly transparent and to lower the hardware costs. As a preparation for tool-based worst-case execution time analysis, the execution time of individual RTTM operations was bounded.
Bibtex
@MASTERSTHESIS{master:hilber,
  author = {Peter Hilber},
  title = {Hardware Transactional Memory for a Real-Time Chip Multiprocessor},
  school = {Vienna University of Technology},
  year = {2010}
}
Download
Get thesis_hilber.pdf - Adobe PDF-format, (701.3105 KB; posted at July 09 2013)


[ main page ] [ back ]