34/2010 : Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults

RR Number

34/2010

Conference

13th IEEE Intl. Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010)

Author(s)

Marcus Jeitler, Jakob Lechner, Andreas Steininger

Abstract

Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

Bibtex

@article{ jeitler:2010-34,
  author =       "Marcus Jeitler and Jakob Lechner and Andreas Steininger",
  title =        "Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults",
  journal =      "13th IEEE Intl. Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010)",
  year =         "2010",
  month =        "Apr."
}

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