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8/2012 : On the Efficient Implementation of a Radiation-Tolerant Event Counter

RR Number
8/2012
Author(s)
Varadan Savulimedu Veeravalli, Andreas Steininger
Abstract
We investigate different approaches of building a radiation-tolerant event counter in an ASIC with a focus on sequential elements. As a first line of defense against bit upsets we propose the use of LFSR based counting, using an increased code space in conjunction with plausibility checking. For the LFSR implementation we study different options on technological, circuit and architectural level. Our evaluations comprise extensive analog-level fault simulations as well as area estimations. While conventional hardening by technology is confirmed to be an efficient approach, our comparison shows that some circuit-level approaches offer specific additional benefits that are discussed. We make two contributions: (1) Presenting a thorough comparison of approaches from the same vantage point, and (2) presenting a fully radiation tolerant solution apart from pure hardening by sizing.
Bibtex
@techreport{ savulimedu veeravalli:2012-8,
  author =       "Varadan Savulimedu Veeravalli and Andreas Steininger",
  title =        "On the Efficient Implementation of a Radiation-Tolerant Event Counter",
  institution =  "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  address =      "Treitlstr. 1-3/182-1, 1040 Vienna, Austria",
  type =         "Research Report",
  year =         "2012",
  number =       "8/2012"
}
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