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10/2012 : A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding

RR Number
10/2012
Conference
2012 International Conference on Application of Concurrency to System Design (ACSD 2012)
Author(s)
Jakob Lechner, Martin Lampacher, Thomas Polzer
Abstract
This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.
Bibtex
@INPROCEEDINGS{6253463,
author={Lechner, J. and Lampacher, M. and Polzer, T.},
booktitle={Application of Concurrency to System Design (ACSD), 2012 12th International Conference on}, 
title={A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding},
year={2012},
month={june},
volume={},
number={},
pages={122 -131},
keywords={Circuit faults;Delay;Encoding;Integrated circuit interconnections;Protocols;Receivers;Registers;asynchronous circuits;delays;dual codes;error correction codes;error detection codes;fault diagnosis;fault tolerance;integrated circuit interconnections;logic design;4-phase dual rail code;GALS-systems;asynchronous circuit design;coding efficiency;data transmission;data word processing;delay-insensitive code;error correcting codes;error detecting codes;fault model;fault tolerance;four-phase dual-rail coding;information redundancy;interconnect architecture;interconnect resource;metastable upset;robust asynchronous interfacing scheme;single-bit errors;system timing;variation tolerance;Asynchronous circuits;Delay-insensitivity;Error correcting codes;Fault-tolerance;GALS;Metastability;},
doi={10.1109/ACSD.2012.29},
ISSN={1550-4808},}
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