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2012 : Effects and Mitigation of Transient Faults in Quasi Delay-Insensitive Logic

Author(s)
Werner Friesenbichler
Abstract
Asynchronous Quasi Delay-Insensitive (QDI) logic offers an improved fault tolerance compared to common synchronous logic. Its delay-insensitive encoding makes QDI circuits not only robust to varying delays but also highly insensitive to transient faults, as such faults likely generate illegal data that is simply ignored. To describe these fault effects in a quantitative manner, a model that includes all assumptions and boundary conditions has to be employed on. With existing models one has to make a trade-off between the level of detail they provide and their complexity. In this work, a new trace based fault model is developed. It covers both unprotected as well as hardened QDI circuits in the necessary level of detail, while still only moderate computational efforts are required to analyze real-world circuits. A trace is the sequence of all signal transitions a circuit receives and generates. As that sequence can be used to synthesize QDI circuits, it only seems to be natural to utilize traces for the description of QDI circuits in a faulty environment as well. Thereby the developed model is used to identify problematic fault scenarios and to derive their relative probability. In the field of QDI circuits, different hardening strategies exist. Based on the insights gained from the trace based fault model, a new method called duplication and rail crosscoupling is derived. The idea is to re-arrange the particular rails of QDI signals in such a way that a transient fault will lead to an illegal code that prevents the fault from being processed. Such a hardened QDI circuit simply waits until the transient fault decays or it deadlocks for indefinite time, but without propagating any data errors. The initial approach was refined and led to the modified DRXS / DRXX / DRS methods, which are investigated in more detail. For a systematic assessment of the proposed hardening methods two complementary approaches using simulation and hardware based fault injection are applied. While related tools are described in literature, these do not appropriately consider the peculiarities of QDI logic. Consequently, two customized fault injection tools are developed, one for fault simulation and one for fault emulation. These tools allow an adequate investigation of transient fault effects, thereby backing up the theoretic results from both the trace based fault model as well as the proposed hardening methods. Several basic test circuits as well as one moderately complex signal processing application are selected to verify the predicted fault tolerance of the different hardening strategies. It is shown that a clever rearrangement of a duplicated QDI circuit helps to improve the tolerance against transient faults significantly, while keeping the hardware overhead low.
Bibtex
@phdthesis{ friesenbichler:2012,
  author =      "Werner Friesenbichler",
  title =       "Effects and Mitigation of Transient Faults in Quasi Delay-Insensitive Logic",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        "2012"
}
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