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26/2012 : A Generic Architecture for Robust Asynchronous Communication Links

RR Number
26/2012
Conference
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012
Author(s)
Jakob Lechner, Robert Najvirt
Abstract
This paper proposes a new generic architecture for building robust communication links for globally asynchronous locally synchronous (GALS) circuits. The general idea is to use delay-insensitive codes along with error detecting codes to provide resilience against transient faults as well as robustness against delay variations. The presented link architecture is completely generic with respect to the chosen handshake protocols (2-phase/4-phase) and the used codes. Thus a specific implementation can be individually optimized regarding features such as performance, power consumption, area complexity or the number of faults that can be tolerated. In order to demonstrate the flexibility of our approach we present several solutions based on 2-phase and 4-phase dual-rail codes combined with either single parity bits or Hamming codes for error detection. In the former case the link provides resilience against single faults, in the latter double faults can be mitigated.
Bibtex
@incollection{,
year={2013},
isbn={978-3-642-36156-2},
booktitle={Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
volume={7606},
series={Lecture Notes in Computer Science},
editor={Ayala, JoséL. and Shang, Delong and Yakovlev, Alex},
doi={10.1007/978-3-642-36157-9_13},
title={A Generic Architecture for Robust Asynchronous Communication Links},
url={http://dx.doi.org/10.1007/978-3-642-36157-9_13},
publisher={Springer Berlin Heidelberg},
author={Lechner, Jakob and Najvirt, Robert},
pages={121-130}
}
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