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55/2012 : Real-Time Runtime Verification on Chip

RR Number
55/2012
Conference
RV 2012
Author(s)
Thomas Reinbacher, Matthias Fuegger, J÷rg Brauer
Abstract
We present an algorithmic framework that allows on-line monitoring of past-time MTL specifications in a discrete time setting. The algorithms allow to be synthesized into efficient observer hardware blocks, which take advantage of the highly-parallel nature of hardware designs. For the time-bounded Since operator of past-time MTL we obtain a time complexity that is double logarithmic in the time it is executed at and the given time bounds of the Since operator. This result is promising with respect to a non-interfering monitoring approach that evaluates real-time specifications during the execution of the system-under-test. The resulting hardware blocks are reconfigurable and have applications in prototyping and runtime verification of embedded real-time systems.
Bibtex
@incollection{,
year={2013},
isbn={978-3-642-35631-5},
booktitle={Runtime Verification},
volume={7687},
series={Lecture Notes in Computer Science},
editor={Qadeer, Shaz and Tasiran, Serdar},
doi={10.1007/978-3-642-35632-2_13},
title={Real-Time Runtime Verification on Chip},
url={http://dx.doi.org/10.1007/978-3-642-35632-2_13},
publisher={Springer Berlin Heidelberg},
author={Reinbacher, Thomas and F├╝gger, Matthias and Brauer, J├Ârg},
pages={110-125}
}
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