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2012 : Selbststabilisierende Byzantinisch Fehlertolerante Takterzeugung in FPGAs

Author(s)
Markus Posch
Abstract
Due to increasing clock-frequencies Systems-on-Chip are nowadays usually designed as GALS-systems (Globally Asynchronous Locally Synchronous). To mitigate the fundamental metastability problems associated with asynchronous communication between uncorrelated clock domains, multi-synchronous GALS is prefered, where some synchronicity between the local clocks is guaranteed. With the ever shrinking feature-sizes and reduced voltage swing, integrated circuits become more susceptible to ionizing particle hits, crosstalk and electromagnetic interference. Mechanisms for tolerance against permanent faults like Byzantine agreement, and self-stabilization against transient faults hence gain importance as well in chip-design. This diploma thesis is in the intersection of distributed fault-tolerant algorithms and VLSI-design. In this thesis it is shown, that a novel algorithm for Byzantine fault-tolerant, self-stabilizing clock-generation, which fulfills the above mentioned properties for modern multi-synchronous GALS-systems, can be correctly implemented. Furthermore the results of the theoretical correctness and performance analysis are validated by experiments on the implementation. The primary goal of this work is the implementation of the distributed clock-generation algorithm and all the required components in VHDL. It is based on mechanisms like e.g. fast glitch-free communication between asynchronous components, stable local ring-oscillators, watchdog-timers with fixed and random timeouts, threshold-modules and the implementation of concurrent communicating asynchronous state machines. All these mechanisms have been implemented in an FPGA-prototype and integrated in a custom test-bench. The predictions of the existing theoretical correctness- and performance analysis could be confirmed by several experiments.
Bibtex
@mastersthesis{Pos12:master,
  author =      "Markus Posch",
  title =       "Selbststabilisierende {B}yzantinisch Fehlertolerante Takterzeugung in {FPGAs}",
  address =     "Treitlstr. 3/3/182-1, 1040 Vienna, Austria",
  school =      "Technische Universit{\"a}t Wien, Institut f{\"u}r Technische Informatik",
  year =        "2012"
}
Download
Get Diplomarbeit_FINAL.pdf - Adobe PDF-format, (2373.2900 KB; posted at July 09 2013)


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