Paper Server : Real-Time Systems Group

Research Reports - 2000

• 2/2000 : Transparent Redundancy in the Time-Triggered Architecture
  G�nther Bauer, Hermann Kopetz
  ICDSN 2000, June 2000, New York, NY, USA
  
  Get rr-02-2000.pdf (271.12KB)
  
  
• 3/2000 : External Clock Synchronization in the Time-Triggered Architecture (TTA)
  G�nther Bauer, Michael Paulitsch
  
  Get rr-03-2000.pdf (407.31KB; this is the main version)
  
  
• 4/2000 : A Comparison of LIN and TTP/A
  Hermann Kopetz, Wilfried Elmenreich, Christoph Mack
  3rd IEEE International Workshop on Factory Communication Systems (WFCS 2000), 6.-8. September 2000, Porto, Portugal
  
  Get rr-04-2000.pdf (84.22KB)
  
  
• 5/2000 : Generation and Analysis of the Codes for TTP/A Fireworks Bytes
  Wolfgang Haidinger, Robert Huber
  
  Get rr-05-2000.pdf (146.38KB)
  
  
• 8/2000 : An Investigation of Membership and Clique Avoidance in TTP/C
  G�nther Bauer, Michael Paulitsch
  19th IEEE Symposium on Reliable Distributed Systems, 16th - 18th October 2000, Nürnberg, Germany
  
  Get rr-08-2000.pdf (77.00KB)
  
  
• 10/2000 : Kostengünstig vernetzen mit TTP/A
  Wilfried Elmenreich
  Markt&Technik -- Wochenzeitung für Elektronik und Informationstechnik, Nr 38/2000
  
  Get rr-10-2000.pdf (79.71KB)
  
  
• 11/2000 : An Introduction to Data Fusion
  Wilfried Elmenreich
  (Document has been replaced by Research Report 47/2001: "An Introduction to Sensor Fusion")
  
  
  
• 12/2000 : Testing and Built-in Self-Test – A Survey
  Andreas Steininger
  Journal of System Architecture
  
  
  
• 13/2000 : Architectural Leadership in the Automotive Industry
  Karl-Thomas Neumann, Hermann Kopetz, Pierre Malaterre, Will Specks
  
  Get rr-13-2000.pdf (315.07KB)
  
  
• 14/2000 : Software Engineering for Real-Time: A Roadmap
  Hermann Kopetz
  Proceedings of the 22nd International Conference on Future of Software Engineering (FoSE) at ICSE 2000, 4th - 11th June 2000, Limerick, Ireland
  
  Get rr-14-2000.pdf (73.97KB)
  
  
• 15/2000 : A Centralized Approach for Avoiding the Babbling-Idiot Failure in the Time-Triggered Architecture
  G�nther Bauer, Thomas Frenning, Anna-Karin Jonsson, Hermann Kopetz, Christopher Temple
  ICDSN 2000, New York, NY, USA
  
  Get rr-15-2000.ps (86.32KB)
  Get rr-15-2000.pdf (338.23KB)
  
  
• 16/2000 : Estimating the Delay Caused by DRAM Refreshes on the Execution Time of Real-Time Tasks
  Pavel Atanassov
  Proceedings of Informatiktage 2000, Specialized Informatics Congress, Gesellschaft für Informatik e.V., Okt. 2000, Bad Schussenried, Germany
  
  Get rr-16-2000.pdf (63.15KB)
  
  
• 17/2000 : Dynamic Worst-Case Execution Time Analysis -- A Comparison Between Two Target Platforms
  Pavel Atanassov
  
  Get rr-17-2000.pdf (77.26KB)
  
  
• 18/2000 : TTP/A: A Low Cost Highly Efficient Time-Triggered Fieldbus Architecture
  Ralf Schlatterbeck, Wilfried Elmenreich
  SAE World Congress 2001, March 2001, Detroit, Michigan, USA
  
  Get rr-18-2000.pdf (160.70KB)
  
  
• 20/2000 : Preliminary Version of the Conceptual Model (DSOS)
  Hermann Kopetz, Michael Paulitsch, et al
  Project Deliverable, Project Dependable Systems of Systems
  
  
  
• 22/2000 : A Comparison of TTP/C and FlexRay
  Hermann Kopetz
  ( HAS BEEN REPLACED BY RESEARCH REPORT 10/2001 )
  
  
  
• 23/2000 : A Universal Smart Transducer Interface: TTP/A
  Hermann Kopetz, Michael Holzmann, Wilfried Elmenreich
  International Journal of Computer System, Science & Engineering
  Vol. 16, No. 2/2001 (Special Issue: ISORC'99)
  
  Get rr-23-2000.pdf (49.86KB)
  
  
• 24/2000 : Supporting Control-Flow-Dependent Execution Times on WCET Calculation
  
  WCET2000 (Deutschsprachige WCET-Tagung, Paderborn, Germany)
  
  Get rr-24-2000.pdf (261.30KB)
  
  
• 25/2000 : Consideration of Optimizing Compilers in the Context of WCET Analysis
  
  Deutsche Informatiktage 2000, Bad Schussenried
  
  Get rr-25-2000.pdf (111.37KB)
  
  
• 26/2000 : Integrating WCET Analysis into a Matlab/Simulink Simulation Model
  Roland Lang, Christopher Temple
  16th IFAC Workshop on Distributed Computer Control Systems, 2000
  
  Get rr-26-2000.pdf (468.96KB)
  
  
• 27/2000 : Application of TTP/A for the Otto Bock Axon Bus
  Roman Obermaisser, Armin Kanitsar
  
  Get rr-27-2000.pdf (1682.09KB)
  
  
• 28/2000 : Implementation of the TTP/A slave protocol on the Atmel ATmega103 MCU
  Philipp Peti, Lukas Schneider
  
  Get rr-28-2000.pdf (2010.15KB)
  
  
• 29/2000 : Tolerating Arbitrary Node Failures in the Time-Triggered Architecture
  Hermann Kopetz, G�nther Bauer, Stefan Poledna
  SAE 2001 World Congress, March 2001, Detroit, MI, USA
  
  Get 2001-01-0677.pdf (61.01KB)
  
  
• 30/2000 : Identifying Bus Failures in a Time-Triggered Communication System Containing Redundant Communication Channels
  Christopher Temple
  The 2000 International Conference on Communications in Computing (CIC'2000), 26th - 29th June 2000, Monte Carlo Resort, Las Vegas, Nevada, USA
  
  Get rr-30-2000.pdf (610.75KB)
  
  
• 31/2000 : Evaluating the Expressive Power of the Real-Time Specification for Java
  Andy Wellings
  Journal of Real-Time Systems, volume 24, number 3, p. 319-359, Kluwer
  
  
  
• 32/2000 : Low-Level Analysis of a Portable Java Byte Code WCET Analysis Framework
  Iain Bate, Guillem Bernat, Greg Murphy
  7th International Conference on Real-Time Computing Systems and Applications, December 2000
  
  Get rr-32-2000.pdf (87.35KB)
  
  
• 33/2000 : Systems Engineering of Time-Triggered Architectures -- The SETTA Approach
  Christian Scheidler, Samuel Boutin, Emmerich Fuchs, G�nter Gr�nsteidl, Yiannis Papadopoulos, Manfred Pisecky, J�rn Rennhack, Ulrich Virnich
  16th IFAC Workshop on Distributed Computer Control Systems, November/December 2000
  
  Get rr-33-2000.pdf (134.08KB)
  
  
• 34/2000 : Facilitating Mobility of Researchers in Europe -- Thoughts on Improvements of Marie-Curie Fellowships
  
  Conference on Investigating in Europe's Human Research Potential, October 2000
  
  Get rr-34-2000.pdf (7.72KB)
  
  
• 37/2000 : Measuring Instruction Timing of the Infineon C167CR Processor
  Pavel Atanassov
  
  Get tr-2000-37-C167_timing_measurements.pdf (202.54KB)
  
  
• 38/2000 : Timing Model of the Infineon C167CR Processor
  Pavel Atanassov
  
  Get tr-2000-38-C167-TimingModel.pdf (93.55KB)
  
  
• 39/2000 : Vom Lenkrad zum Joystick - Replacing the Steering Wheel by a Joystick
  Christoph Scherrer, Andreas Steininger
  Elektrotechnik und Informationstechnik (e&i)
  
  
  
• 40/2000 : Periodic Node Shutdown in a Fail-Silent Architecture – Risk or Rescue?
  Christoph Scherrer, Andreas Steininger
  4th World Multiconference on Systemics, Cybernetics and Informatics (SCI2000)
  
  
  
• 41/2000 : How Does Resource Utilization Affect Fault Tolerance?
  Christoph Scherrer, Andreas Steininger
  International Symposium on Defect and Fault Tolerance in VLSI Systems