MARS - Maintainable Real-Time System
The MARS architecture satisfies the requirements of predictability,
testability, fault-tolerance, and ease of evaluation. The following
paragraphs are intended to give anb impression of what the MARS system
is all about. For further details, check out the papers on our
paper server.
[ System Architecture ]
[ Task Model ]
[ Design Environment ]
[ Hardware ]
[ Operating System ]
System Architecture
A MARS computer system consists of one or
more clusters, which are distributed systems composed of single board
computers, called components, connected by a real-time bus. All the
components of a cluster maintain a global time base, which allows them
to synchronize their actions and to use a deterministic,
collision-free time-division, multiple-access protocol to control bus
access.
Task Model
Each component periodically executes a fixed set of tasks. These tasks
communicate with each other and the environment solely by
messages. They receive all needed messages before starting execution
and send output messages after having finished. To achieve
predictable timing behavior on the components, tasks execute in time
slots, which they have been assigned before runtime. Similarly, each
message is assigned a dedicated transmission slot on the bus.
Design Environment
The architecture relies on the availability of a design environment
with a preruntime scheduler and an analysis of task execution times to
achieve a guaranteed, predictable timing behavior. During the
development of an application the user develops complex real-time
transactions, which specify the system behavior, into sets of simple,
cooperating tasks that exchange messages. The tasks' execution times
together with the messages are input to the off-line scheduler. The
scheduler produces both a task schedule and an assignment of messages
to bus slots, which together meet all synchronization, communication,
and timing requirements imposed by the specification.
Hardware
The underlying hardware was designed to ensure the predictability of
the timing behaviour of application tasks. To avoid problems posed by
caching and instruction pipelining, the current MARS implementation
uses processors of Motorola's 68000 family, which have fixed
instruction execution times. Each component contains two processors,
which are coupled over a FIFO. This design shelters the application
tasks from the DMA overhead of the communication controllers:
Application tasks execute on one processor, while the low-level
details of network communication are handled by the second processor.
Operating System
The operating system employs a microkernel architecture:
Only the most basic functions are implemented in the kernel, whereas
most of the functionality has been put into dedicated system tasks,
thus facilitating the prediction of the timing behavior.
The only interrupt present is the periodic
clock interrupt, which marks the beginning and end of CPU and bus
slots. Its execution time is a known parameter.
The combination of predictable hardware, predictable operating system,
task structure, and the preruntime scheduling permits the use of
source-code analysis techniques to predict the timing behaviour of
a real-time application.
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This page was last updated on Sep 30 1997 by webmaster@vmars.tuwien.ac.at