This page provides a brief overview of all past and present research projects conducted by the group. Follow the links to obtain more detailed information!
The main objectives in the design of MARS are predictability, testability, design for peak load, and fault tolerance. The project resulted in the development and successful implementation of a prototype system, including a distributed real-time operating system, a programming language supporting the analysis of the worst case execution time, and some demo applications.
For more detailed information on MARS look at the MARS page.
In the context of the PDCS projects, extensive fault-injection experiments with the MARS prototype hardware, operating system, and compiler were undertaken. Chalmers University of Technology (located in Gothenburg, Sweden) conducted heavy-ion radiation experiments, LAAS-CNRS (Toulouse, France) did pin-level fault-injections, and our group performed electro-magnetic interference (EMI) experiments.
There is a home page for the PDCS-2 project.
There are, in fact, two versions of the protocol: TTP/C for safety-critical applications requiring a high level of fault tolerance, and TTP/A for fieldbus applications, with a focus on low cost while preserving the favorable temporal properties. Prototypes for both protocol version, which have been developed together with our industrial partners, exist.
The TTP pages tell you more about both protocol versions.
Seven industrial partners from the European automotive industry and two universities were involved in the project. The project has started on January 1st 1996 and ended on December 31st 1998. The immediate goals of the project were the definition of an architecture for x-by-wire systems and the implementation of prototype to demonstrate the feasibility of the concepts. Further goals were the establishment of the preconditions for mass production and the preparation of standardization activities.
Look at the x-by-wire home page for the project summary and objectives, and for public project documents.
In December 1998 a final workshop together with the partners of the TTA project has taken place in Vienna.
A key component of this architecture was a communication controller executing the time-triggered protocol (TTP). This VLSI component was accompanied by a comprehensive systems engineering environment offering user-friendly tools for design, application programming support, and safety analysis. To prove the approach, an evaluation of TTA and its accompanying systems and safety engineering environment in a realistic setting was needed. The project encompassed such an evaluation for three typical industrial applications, one from each of the three participating sectors (automotive, aerospace, railway).
Here you can find an overview of the TTA project.
In December 1998 a final workshop together with the partners of the X-By-Wire project has taken place in Vienna.
In fault-tolerant applications, which have to provide the fail-operational property, the active replication of computational nodes, communication structures, and sensors/actuators is a common solution. The paradigm of event-triggered communication and task activation makes the cost effective implementation of active replication of system components a difficult task. As a solution, the time-triggered paradigm was developed. The Time-Triggered Architecture (TTA) is the consequent extension of the time-triggerd paradigm into the field of distributed safety-critical real-time systems.
The resulting architecture includes a fault-tolerant real-time communication system (TTP/C), a time-triggered field bus (TTP/A) and a time-triggered operating system (TTOS). The presentation of this architecture is the goal of a demonstration object built by the Real-Time Systems Group at the Vienna University of Technology.
Here you can find an overview of the Time-Triggered Architecture Demonstrator. This link will show you some pictures of the TTA Demonstrator in the laboratory and at the FTCS '98 in Munich, Germany.
Our measuring system page tells more.
The project consortium consists of seven project partners and three associate members. DeVa started on December 15th 1995. It is scheduled for a duration of 36 months.
Further information about DeVa can be found on the DeVa home page.
CaberNet consists of more than 40 member nodes which are spread all over Europe. The activities of the network are coordinated and administered by eleven managing nodes. CaberNet services include, but are not limited to, the Technical Reports and Abstract Service, a Member Projects Database, the Distributed Distributed Computing Curriculum, the Technological Roadmap, and the Industrial Liasion Database. CaberNet supports and organizes visits, research exchanges and workshops for member nodes.
For more details on CaberNet visit the CaberNet home page.
Partners:
For more details on DSoS visit the DSoS home page.
Fault-tolerance is achieved by replication of functional units. A fault-tolerance layer cares for management of these replicated units and provides a single (agreed) value to consumer applications thus providing transparency in the value domain: consumer applications only receive a single value irrespective of the number of producer replicas. Besides this, the time-triggered architecture also allows for transparency in the time domain, i.e., the timing of consumer applications does not need to be changed if the number of producer applications changes (in order to tolerate more / less faults). This can be achieved by definig a set of rules that govern the application design process.
Within this project, the software needed to provide transparency in the time domain will be designed and implemented using a dedicated TTP/C communication controller chip. Further, the application design guidlines to establish transparency in the time domain will be defined. Finally, a series of fault-injection experiments will be performed to provide evidence for the correctness of the design.
Documents:
The key characteristic of time-triggered, distributed real-time systems is that all significant events, including tasks and messages, do not occur at random points in time, but rather have to adhere to a pre-determined schedule.
This approach initially requires a larger design effort than classical, event-triggered systems; once built, however, time-triggered systems have several advantages, such as predictability concerning their real-time behaviour, which make them uniquely suited for complex, safety-critical real-time systems.
The contribution from TU Vienna to the SETTA project is the development and implementation of a performance analyzing tool. This tool calculates the worst case execution time (WCET) of a program from the source file during the compilation process. The knowledge of the WCET of a program is crucial for the design of safety-critical real-time systems.
For more information please have a look at the SETTA archive.
A prototype micro-programmable version of a TTP/C controller chip has been designed an implemented during the ESPIRIT project TTA. It is objective of the "Fault Injection into the Time-triggered architecture" - FIT project to experimentally validate the system concepts of TTA, taking this prototype TTP/C controller chip as basis. In particular it is planed to
Project Partners:
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Carinthia Tech Institute |
Villach |
www.cti.ac.at |
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TU Wien |
Vienna |
www.vmars.tuwien.ac.at |
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TTTech Computertechnik GmbH |
Vienna |
www.tttech.com |
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Czech Technical University |
Prague |
www.cvut.cz |
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Universidad Politecnica de Valencia |
Valencia |
www.disca.upv.es |
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Chalmers University of Technology |
Gothenburg |
www.ce.chalmers.se |
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AB Volvo |
Gothenburg |
www.vovlo.se |
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Motorola GmbH |
Munich |
www.motorola.com |
SoftWare Implemented Fault Injection (SWIFI) is going to be performed by TU WIEN. In order to achieve a good reproducibility of experiments on different TTP/C implementations, by SWIFI is planed to corrupt only the data structures that must be accessible in any implementation, i.e., MEDL and CNI. The data fields within the host will be corrupted to detect the error-detection coverage of the end-to-end detection protocols.
PAMELA is a Critical Technology project, aimed at selecting and preparing the underlying technologies, concepts and standards for future implementation of Integrated Modular Aircraft Electronics, which covers Cockpit avionics and utilities, crew and passenger services and communications. The new generation of standards shall take into account the accelerating progress of Information Technology in order to define a framework for future aircraft electronics for years 2005 to 2020.
The PAMELA consortium is made up of airframers, equipment suppliers and universities, in order to: define the overall requirements; review and assess the available or emerging technologies; select the relevant technologies, define the new concepts for architecture and integration, examine specifics of regional and helicopter applications compared with air transport; develop experiments to solve issues raised concerning technologies; specify and prototype tools and methods for development; prepare a framework and drafts for new standards to be created.
The focus of the TTSB project is to work out the concepts for a modern and cost-effective fieldbus. The TTP/A fieldbus has been chosen to be sophisticated to fullfill the needs of typical applications in the automotive and automation domain:
The NEXT TTA project enhances the structure, functionality and dependability of the time-triggered architecture (TTA) to meet the austere cost structure of the automotive industry, while satisfying the rigourous safety requirements of the aerospace industry. By placing the safety-relevant algorithms, that are formally analyzed, into intelligent replicated star couplers, NEXT TTA reduces the cost and generalizes the failure assumptions of the node computers. Event-triggered communication services are integrated into the TTA to increase the required flexibility. The synchronous programming environment LUSTRE and its tool set are extended for the TTA and automated worst-case-execution-time analysis is explored. CORBA compliant interfaces are provided in order to make TTA systems interoperable with the open information infrastructure. The limits of implementing the TTA with COTS components in the gigabit range are investigated.
The Hard Real-Time Corba (HRTC) project identifies the requirements for making CORBA suitable for Real-Time communication as it is needed e.g. in controlling applications.
In order to reach the official project homepage with detailed information about this project just click on the headline of this section.
Objectives
Coordinate the R&D effort in the area of Advanced Real-time Systems so as to:
The focus of the CoMa project is to elaborate concepts and methods for the configuration and maintenance of the time-triggered fieldbus system TTP/A.
The requirement for configuration support can be justified by three arguments: First, an automatic or semi-automatic configuration saves time and therefore leads to better maintainability and lower costs. Second, the necessary qualification of the person who sets up the system is lower when the overall system is easier configured. Third, the number of configuration faults will decrease, since monotone and error-prone tasks like looking up configuration parameters in heavy manuals are done by the computer.
A fully automatic configuration will in most cases only be possible if the functionality of the system is reduced to a manageable subset. For more complex applications consulting a human mind is inavoidable. Thus, we distinguish two use cases, the automatic set-up of simple subsystems and the computer-supported configuration of large distributed systems.
Furthermore, developers expect diagnostic services, which are deterministic, reproducible, and do not interfere with realtime services.
The CoMa project was funded by the Hochschuljubiläumsstiftung der Stadt Wien as project number H-965/2002.
The Rapid Prototyping Kit Project is a cooperative project between TTTech Computertechnik AG and the Institut für Technische Informatik. Central aim of this project was the development of a Rapid Prototyping Kit (RPK) for creating time-triggered control applications, whereas the focus of the institute of technology was primarily placed on the creation of testing strategies for the RPK. More details on this project can be found on the project page.
The FIT-IT project "Rapid Prototyping Kit" is funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No 806033.
The MoDECS project aims at delivering a radical innovation in the model-based construction of distributed embedded control systems: MoDECS should significantly contribute to a shift from a platform-oriented towards a domain-oriented, platform-independent development of composable, distributed embedded control systems. MoDECS is a cooperative project between AVL List GmbH, MagnaSteyr Fahrzeugtechnik GmbH & Co KG, University of Salzburg, and the Institut für Technische Informatik. More details on this project can be found on the project page.
The FIT-IT project MoDECS is funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No 807144.
Dependable embedded real-time systems constitute a fundamental enabling technology for the information society. As our reliance on embedded systems, for safety/service critical as well as commodity applications, is continually growing, their economic impact reaches far beyond their immediate market size. For the next generation of dependable embedded real-time systems, the rapidly growing system requirements also result in enormous increases of system complexity, necessitating reuse of pre-validated hardware and software components and functional blocks for both design and certification purposes. Thus, the major objective of the DECOS project is to research the compositional system framework and to develop a set of generic hardware and software components usable on various platforms including the Time-Triggered Architecture. The integrated project DECOS will develop the basic enabling technology to move from a federated distributed architecture to an integrated distributed architecture in order to reduce development, validation and maintenance costs, and increase the dependability of embedded applications in various application domains. DECOS plans to develop technology invariant software interfaces and encapsulated virtual networks with predictable temporal properties such that application software can be transferred to a new hardware and communication base with minimal effort (legacy reuse). DECOS methodology and tools will be evaluated over the domains of automotive, aerospace and control applications. DECOS builds upon the foundations established in previous European research projects (e.g. NextTTA, FIT, TTA, SETTA, RISE, X-By-Wire). The components and tools developed within DECOS will cover: cluster design, middleware and code generators, validation and certification as well as systems-on-a-chip (SoCs) for high dependability applications..
The long-term objective of ARTIST2 is to build a durable European research community on Embedded Systems Design, by integrating the topics, teams, competencies, from 7 essential topics: Modelling and Components, Hard Real-Time, Adaptive Real-Time, Compilers and Timing Analysis, Execution Platforms, Control for Embedded Systems, Testing and Verification. The NoE will act as a Virtual Centre of Excellence in the area of Embedded Systems Design. It is structured into clusters (virtual teams), corresponding to these essential topics. The integration into joint research activities will occur at two levels: Integration within clusters. Currently, the efforts on the identified topics are fragmented, and there is no European research team that would gather the sufficient critical mass needed. The integration of a topic is a first step towards integrating the area as a whole. Integration between cluster topics to create the multi-disciplinary community that will pilot the embedded systems design area. This will be achieved through integration activities that will bring together teams from different clusters. The Joint Programme of Reseach Activities includes research both within the clusters, and between clusters. Intra-cluster research aims to create critical mass and excellence on each essential topic. Inter-cluster research aims to integrate the area as a whole. The implementation of the Joint Programme of Research Activities is supported by the Joint Programme of Integrating Activities, including research platforms, mobility of personnel, and a common communication infrastructure. A central mission for the NoE is spreading excellence in the area, through an ambitious Joint Programme of Activities for Spreading Excellence, including Education and Training, Dissemination and Communication, Industrial Liaison, and International Collaboration. .
It is the goal of the TT-Ethernet project to develop a time-triggered (TT) Ethernet with predictable temporal performance and strong fault-isolation for use in safety-critical real-time control systems in automotive, avionics and railway domains and at multimedia systems. The TT-Ethernet is fully compatible with the current Ethernet standard as proposed by IEEE and supports the parallel operation of classic Ethernet nodes and TT-Ethernet nodes within the same cluster. The set of Ethernet messages is partitioned into two classes, the classic event-triggered (ET) Ethernet messages and the high-priority time-triggered Ethernet messages. TT messages are transported through the proposed new Ethernet switch with an a priori known constant delay and minimal jitter (in the sub-microsecond range). If an ET message is in the way of a TT message, the ET message is preempted. The TT messages can be used to synchronize the clocks in the nodes to a high precision and thus establish a sparse global time base. Based on this global time a schedule for the transmission of the TT messages can be established - either statically at compile time or dynamically at run time. The newly designed Ethernet switch will contain special algorithms to support strong fault isolation. By extending the time-triggered technology to high-speed Ethernet based systems, it is expected to significantly extend the market for time-triggered systems to new application domains in the control field and in the multimedia field. It is anticipated that this research project will form part of the technology base for the next generation of time-triggered products.
The FIT-IT project TTEthernet is funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No 808197.
The FIT-IT project Te-DES is funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No .